When designing a single-transistor-amplifier stage; be it an AF, RF, IF, whatever project, one must always take into account the gain of the transistor in question and design for it accordingly. It’s best not to attempt to utilise the full amount of available gain as the transistor will probably saturate and cause distortion. In fact a tri-stage amplifier with negative-feedback, (The subject of a later article maybe.) with only half the available gain of each transistor used will produce a much better and less distorted output than a single-transistor stage utilising all of the available gain.

For now, however, I’m going to concentrate on just a single-transistor stage, and on correctly biasing the transistor’s base proportional to its base/collector.

Let’s assume that our subject transistor has a voltage-gain of 20, and a Vb(max) of 3.3V. Let’s place it in circuit:

Ignoring the type and strength of input signal as far as this example is concerned, we intend to bias the base of the transistor from the supply rails using a straightforward potential divider (R1 & 2). We know that the base voltage must not exceed 3.3V, and we’re running the circuit from a 6 Volt rail. We use the equation V=Vin (+Vcc in this case, using a NPN transistor.) X R2 / (R1 X R2). In the example above, (Which is an example only rather than a functional circuit.) I’ve taken a guess and used a 1K negative resistor (R2) and a 2.7K resistor (R1) to the rail. This gives a working base voltage of 2.223 Volts. In most cases we’d tweak that voltage, by altering the resistance values, to as near 0.7 Volts as possible. (The transistor’s transconductance threshold, assuming that we are using a silicon rather than a germanium transistor.) For this example we’ll leave it at 2.223 Volts.

Note the use of resistances in the kilohm range: This is for the purpose of limiting the base current. Although we haven’t specified a current for the input signal we’re assuming that it’s in the several-tens-of-milliamperes range. When dealing with even smaller input signal currents use higher resistance to limit the biasing current further so as not to interfere with the input signal.

We can work out the base-bias current precisely using Ohm’s Law: I=V/R; 6 volts divided by (R1 + R2 = 3700Ohms) = 1.62 milliamperes: We’d therefore be looking for a gain of about 10, driving the transistor at half-available-gain, so it would be fair to say to use a total DC resistance of 100 Ohms in the emitter circuit, and a total DC resistance of 270 Ohms in the collector circuit, ignoring any reactance from any decoupling capacitor (Such as C3 in the second circuit.) in the emitter circuit.

Looking at that second circuit we note that there are DC decoupling capacitors (C1 & C2) on the input and output of the stage: these are included to prevent any DC component bleeding back into the stage before, as well as bleeding off from the collector circuit into the following stage. Note that I’ve sketched in a decoupling capacitor into the base circuit using a broken line: This may or may not be a good idea depending upon many factors; and that’s well beyond the scope of this post.

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